This application claims the benefit of Korean Patent Application No. 2001-30702, filed on Jun. 1, 2001 in Korea, which is hereby incorporated by reference for all purposes as if fully set forth herein.
1. Field of the Invention
The present invention relates to an array substrate of a liquid crystal display (LCD) device and more particularly, to a method of manufacturing an array substrate having drive integrated circuits (drive ICs).
2. Discussion of the Related Art
Due to a rapid development in information technology, display devices have evolved into instruments that can process and display a great deal of information. Flat panel display devices, which have properties of being thin, low weight and low power consumption, such as liquid crystal display (LCD) devices, have been developed. The LCD device is widely used for notebook computers and desktop monitors, etc. because of its superior resolution, color image display and quality of displayed images. The LCD device consists of an upper substrate, a lower substrate and a liquid crystal layer disposed between the upper and lower substrates. The LCD device uses an optical anisotropy of liquid crystal and produces an image by controlling light transmissivity by varying the arrangement of liquid crystal molecules, which are arranged by an electric field.
One substrate of the LCD device includes a thin film transistor that acts as a switching device. An LCD device, which includes the thin film transistor, is referred to as an active matrix liquid crystal display (AMLCD) and it has a high resolution and can display an excellent moving image. Amorphous silicon is widely used as an active layer of the thin film transistor because amorphous silicon can be formed on a large, low cost substrate such as glass.
The LCD device also includes a drive integrated circuit (drive IC) that controls the thin film transistor. Unfortunately, amorphous silicon does not form a suitable active layer for the drive IC, which usually includes CMOS (complementary metal-oxide-semiconductor) devices that require crystalline silicon as active layers. Because of this, the drive IC is usually connected to the array substrate using a TAB (tape automated bonding) system. This adds significant cost to the LCD device.
Because of limitations of amorphous silicon, an LCD device that incorporates polycrystalline silicon as an active layer is being researched and developed. Polycrystalline silicon is highly beneficial because it is much better suited for use in the drive IC than amorphous silicon. Polycrystalline silicon thus has the advantage that the number of fabrication steps could be reduced because a thin film transistor and a drive IC could be formed on the same substrate, eliminating the need for TAB bonding. Furthermore, the field effect mobility of polycrystalline silicon is 100 to 200 times greater than that of amorphous silicon. Polycrystalline silicon is also optically and thermally stable.
FIG. 1 is a schematic block diagram showing an array substrate of a conventional liquid crystal display (LCD) device having drive integrated circuits (drive ICs). In FIG. 1, the LCD device includes a driving portion 3 and an image portion 4 on a substrate 2. The image portion 4 is located in the center of the substrate 2, and the gate driving portion 3a and the data driving portion 3b are located in the left and top regions of the substrate 2. In the image portion 4, a plurality of gate lines 6 are disposed horizontally and a plurality of data lines 8 are disposed vertically. The gate lines 6 and the data lines 8 cross each other to define a plurality of pixel regions. A pixel electrode 10 is disposed in the pixel region and a thin film transistor xe2x80x9cTxe2x80x9d, switching device, is formed in the form of matrix at each crossing of the gate lines 6 and the data lines 8. Each thin film transistor xe2x80x9cTxe2x80x9d is connected to each pixel electrode 10. The gate driving portion 3a, which includes a plurality of drive ICs, supplies an address signal to the gate lines 6, and the data driving portion 3b, which also includes a plurality of drive ICs, supplies an image signal to the data lines.
The gate driving portion 3a and the data driving portion 3b are electrically connected to an outer control circuit (not shown) with signal input terminals 12 which are formed on one edge of the substrate 2, so that the outer control circuit (not shown) controls the drive ICs of the gate driving portion 3a and the data driving portion 3b. The outer control circuit (not shown) applies signals to the gate and data driving portions 3a and 3b through the signal input terminals 12.
As stated above, the gate driving portion 3a and the data driving portion 3b includes drive ICs having a CMOS (complementary metal-oxide-semiconductor) transistor as an inverter which changes a direct current into an alternating current. The CMOS transistor comprises an n-channel MOS transistor, in which electrons are the majority carriers, and a p-channel MOS transistor, in which holes are the majority carriers. Therefore, in n-channel MOS transistor, most of the current is carried by negatively charged electrons and in p-channel MOS transistor, most of the conduction is carried by positively charged holes.
The thin film transistor xe2x80x9cTxe2x80x9d of the image portion 4 and CMOS transistor (not shown) of the driving portion 3 use polycrystalline silicon as an active layer, and thus can be formed on the same substrate 2.
FIGS. 2A and 2B are cross-sectional views showing conventional thin film transistors posited in an image portion and in a driving portion, respectively. The thin film transistors have a top-gate type structure in which a gate electrode is formed on a semiconductor film.
In FIG. 2A, i.e., in the image portion, a buffer layer 14 is formed on a transparent substrate 1. A semiconductor layer 16 is formed on the buffer layer 14, and the semiconductor layer 16 consists of four portions, i.e., an active layer 16a in the middle of the semiconductor layer 16, source and drain regions 16c and 16d in both ends of the semiconductor layer 16, and lightly doped drain (LDD) region 16b disposed between the active layer 16a and the source region 16c or the active layer 16a and the drain region 16d. The LDD region 16b includes impurities of low density and prevents leakage current of an off-state, that is, applying reverse bias to thin film transistor. A gate insulator 18 is formed on the active layer 16a and a gate electrode 20 is formed on the gate insulator 18. An inter layer insulator 24 is formed the gate electrode 20 and covers the gate electrode 20. The inter layer insulator 24 has first and second contact holes 22a and 22b exposing the source and drain regions 16c and 16d, respectively. Next, source and drain electrodes 26 and 28 are formed on the inter layer insulator 24, and the source and drain electrodes 26 and 28 are connected to the source and drain regions 16c and 16d through the first and second contact holes 22a and 22b, respectively. A passivation layer 32 is formed on the source and drain electrodes 26 and 28, and covers the source and drain electrodes 26 and 28. The passivation layer 32 has third contact hole 30 exposing the drain electrode 28. A pixel electrode 34 is formed on the passivation layer 32 and the pixel electrode 34 contacts the drain electrode 28 through the third contact hole 30 of the passivation layer 32.
The source and drain regions 16c and 16d of FIG. 2A include donor impurities from group V of the periodic table and most of current is carried by electrons. Accordingly, the thin film transistor xe2x80x9cAxe2x80x9d of FIG. 2A is n-channel MOS transistor.
As shown in FIG. 2B, CMOS transistor in the driving portion comprises n-channel MOS transistor xe2x80x9cBxe2x80x9d and p-channel MOS transistor xe2x80x9cCxe2x80x9d. In FIG. 2B, a buffer layer 14 is formed on a transparent substrate 1. Next, semiconductor layers 40 and 42 are formed on the buffer layer 14. The semiconductor layer 40 of the n-channel MOS transistor xe2x80x9cBxe2x80x9d consists of four portions, i.e., an active layer 40a in the middle of the semiconductor layer 40, n+ source and drain regions 40c and 40d in both ends of the semiconductor layer 40, and lightly doped drain (LDD) region 40b disposed between the active layer 40a and the n+ source region 40c or the active layer 40a and the n+ drain region 40d. On the other hand, the p-channel MOS transistor xe2x80x9cCxe2x80x9d is not much affected by hot carrier and leakage current compared with the n-channel MOS transistor xe2x80x9cBxe2x80x9d. Therefore, semiconductor layer 42 of the p-channel MOS transistor xe2x80x9cCxe2x80x9d comprises three portions of an active layer 42a, a p+ source region 42b, and a p+ drain region 42c. Gate insulators 44a and 44b are formed on the active layers 40a and 42a. Gate electrodes 46a and 46b are formed on the gate insulators 44a and 44b. An inter layer insulator 24 is formed the gate electrodes 46a and 46b and covers the gate electrodes 46a and 46b. The inter layer insulator 24 has first to fourth contact holes 47a, 47b, 47c and 47d exposing the source and drain regions 40c, 40d, 42b and 42c, respectively. Next, source and drain electrodes 50a, 52a, 50b and 52b are formed on the inter layer insulator 24, and the source and drain electrodes 50a, 52a, 50b and 52b are connected to the source and drain regions 40c, 40d, 42b and 42c through the first to fourth contact holes 47a, 47b, 47c and 47d, respectively. A passivation layer 32 is formed on the source and drain electrodes 50a, 52a, 50b and 52b, and covers the source and drain electrodes 50a, 52a, 50b and 52b. 
A manufacturing process of the conventional thin film transistors will be described in detail with reference to the attached FIG. 3.
FIG. 3 is a flow chart showing the process of manufacturing a conventional array substrate including the thin film transistors.
In the first step, an insulating substrate is prepared (ST1). The insulating substrate is made of transparent material such as glass. Here, a buffer layer is formed on the insulating substrate to about a thickness of 3,000 xc3x85. The buffer layer is formed of an inorganic material such as silicon nitride (SiNx) and silicon oxide (SiO2).
In the second step, semiconductor layers are formed (ST2). First, amorphous silicon is deposited on the insulating substrate having the buffer layer to about a thickness of about 550 xc3x85. After the deposited amorphous silicon passes through a dehydrogenation step, the dehydrogenated amorphous silicon is crystallized into polycrystalline silicon by a laser. Then, the polycrystalline silicon is patterned by using a first mask and the semiconductor layers are formed.
In the next step, gate insulators and gate electrodes are formed (ST3). At this time, a silicon nitride of about 800 xc3x85 is deposited on the substrate having the semiconductor layers thereon and a refractory metal such as molybdenum (Mo) is deposited on the silicon nitride to a thickness of about 2,000 xc3x85. Continuously, the silicon nitride and the molybdenum are patterned through a second mask process, and gate insulators and gate electrodes are formed on the semiconductor layers.
In the following step, n+ source and drain regions are formed (ST4). Here, lightly doped drain (LDD) regions are also formed. Nxe2x88x92 ions are injected into one exposed semiconductor layer using the gate electrode as a mask. Continuously, a photoresist pattern, which covers the gate electrode and the nxe2x88x92 ion doped semiconductor layer near the gate electrode, is formed through a third mask process and n+ ions are subsequently injected into the semiconductor layer, which is not covered with the photoresist pattern. At this time, a photoresist pattern entirely covers the other semiconductor layer. The n+ ions doped semiconductor layers are n+ source and drain regions, and the nxe2x88x92 doped semiconductor layers are LDD regions. Here, the semiconductor layer, which does not include ions, becomes an active layer. Next, the photoresist patterns are removed.
In the next step, p+ source and drain regions are formed (ST5). P+ ions are injected into the other exposed semiconductor layer using the gate electrode as a mask. At this moment, a photoresist pattern is formed on the semiconductor of ST4 through a fourth mask process and entirely covers the semiconductor. The p+ ions doped semiconductor layers are p+ source and drain regions, and the semiconductor layer, which does not include ions, becomes an active layer. Then, the photoresist pattern is removed.
Next, an inter layer insulator is formed (ST6). The inter layer insulator is made of an inorganic material such as silicon nitride and silicon oxide, and has a thickness of about 7,000 xc3x85. The inter layer insulator is patterned through a fifth mask process and contact holes, which exposes the source and drain regions, are formed.
In the following step, source and drain electrodes are formed (ST7). Metals, such as molybdenum (Mo) and aluminum-neodymium (AlNd) are sequentially deposited on the inter layer insulator about 500 xc3x85 and about 3,000 xc3x85 thick, respectively. The Mo and AlNd are etched through a sixth mask process, and source and drain electrodes, which are connected to the source and drain regions through the contact holes, are formed.
In the next step, a passivation layer is formed (ST8). Silicon nitride is deposited to about 4,000 xc3x85 on the substrate having source and drain electrodes thereon. After the silicon nitride is annealed, the silicon nitride is patterned through a seventh mask process, and so a drain contact hole is formed. The drain contact hole exposes the drain electrode of the image portion. The annealing process is accomplished at about 380 degrees Celsius in a nitrogen atmosphere. For the annealing process, hydrogen within the passivation layer is driven downward.
In the last step, a pixel electrode is formed (ST9). The pixel electrode exists only in the image portion. A transparent conducting material, such as indium-tin-oxide (ITO), is deposited on the passivation layer. The transparent conducting material is patterned through an eighth mask process, and so the pixel electrode, which contacts the drain electrode through the drain contact hole, is formed.
In the above process, steps of forming n+ source and drain regions and p+ source and drain regions are illustrated in FIGS. 4A to 4C and FIGS. 5A to 5C. FIGS. 4A to 4C are cross-sectional views of a manufacturing process of thin film transistor formed in a first region xe2x80x9cAxe2x80x9d of the image portion and FIGS. 5A to 5C are cross-sectional views of a manufacturing process of thin film transistors formed in second and third regions xe2x80x9cBxe2x80x9d and xe2x80x9cCxe2x80x9d of the driving portion.
As shown in FIGS. 4A and 5A, an nxe2x88x92 ion doping is accomplished on the substrate 1, which includes semiconductor layer 16, 40 and 42, gate insulators 18, 44a and 44b, and gate electrodes 20, 46a and 46b in each region, using gate electrodes 20, 46a and 46b as mask. Here, nxe2x88x92 ions are injected into the exposed semiconductor layer 16e, 40e and 42e. The center portions of the semiconductor layers, which do not include impurities, become active layers 16a, 40a and 40b. 
In FIGS. 4B and 5B, first photoresist patterns 21, 47 and 48 are formed using a photolithography process. The first photoresist patterns 21 and 47 of the first region xe2x80x9cAxe2x80x9d and the second region xe2x80x9cBxe2x80x9d cover the gate electrodes 20 and 46a and the nxe2x88x92 ion doped semiconductor layers 16e of FIG. 4A and 40e of FIG. 5A near by the gate electrodes 20 and 46a while the first photoresist pattern 48 of the third region xe2x80x9cCxe2x80x9d covers the gate electrode 46b and all the semiconductor layer 42a and 42e. Subsequently, n+ ion doping, having higher density than nxe2x88x92 ion doping of FIGS. 4A and 5A, is performed on the substrate 1, and the exposed semiconductor layers result in n+ source and drain regions 16c, 16d, 40c and 40d including n+ ions. The covered nxe2x88x92 doped semiconductor layers become lightly doped drain (LDD) regions 16b and 40b. After that, the first photoresist patterns 21, 47 and 48 are removed.
Next, in FIGS. 4C and 5C, second photoresist patterns 22 and 49 are formed through another photolithography process. The second photoresist pattern 22 of the first region xe2x80x9cAxe2x80x9d covers the gate electrode 20, the n+ source and drain regions 16c and 16d, and the LDD region 16b. The second photoresist pattern 49 of the second region xe2x80x9cBxe2x80x9d covers the gate electrode 46a, the n+ source and drain regions 40c and 40d, and the LDD region 40b. And p+ ion doping is carried out, using the second photoresist patterns 22 and 49 as mask. Then, p+ ions are injected into the exposed semiconductor layer, and p+ source and drain regions 42b and 42c are formed. The second photoresist patterns 22 and 49, subsequently, are removed.
As stated before, two photolithography processes are required in order to form conventional CMOS thin film transistors, which is composed of n-channel MOS transistor and p-channel MOS transistor. The photolithography process includes several steps of coating photoresist, exposing through a mask and developing the photoresist. Therefore, as photolithography processes are added, fabricating time, costs, and failure may be increased.
On the other hand, polycrystalline silicon is used as the active layers in the above thin film transistors. Polycrystalline silicon can be formed by depositing amorphous silicon on a substrate, such as by plasma enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD), and then crystallizing that amorphous silicon into polycrystalline silicon. There are a number of different methods of crystallizing amorphous silicon into polycrystalline silicon, including solid phase crystallization (SPC), metal induced crystallization (MIC), and laser annealing.
However, polycrystalline silicon formed by the above methods has a lot of crystal grains and grain boundaries. These grains and boundaries interrupt the carrier movement and cause the deterioration of the device. Further, if the grains are larger and the grain boundaries are regularly distributed within the polycrystalline silicon, the field effect mobility becomes larger. In view of these grains and grain boundaries, a silicon crystallization method that produces large grains is important.
Recently, a new method of crystallization, often referred to as sequential lateral solidification (SLS), has been researched. The SLS method takes advantage of the fact that silicon grains grow laterally from the boundary between liquid phase silicon and solid phase silicon. The SLS method can increase the size of the silicon grains that grow by controlling the energy intensity of a laser beam and the irradiation range of the laser beam (reference, Robert S. Sposilli, M. A. Crowder, and James S. Im, Mat. Res. Soc. Symp. Proc. Vol. 452, 956xcx9c957, 1997). This enables thin film transistors having channel areas of single crystalline silicon.
FIG. 6 is a graph showing a grain size in accordance with the energy density of laser beam, and FIGS. 7A to 7C are cross-sectional views of the silicon films for explaining the mechanism of forming polycrystalline silicon film composed of grains depending on the energy density of laser beam. The energy density of a laser beam for each region depends on the laser apparatus used. As shown in FIGS. 7A to 7C, a buffer layer 102 and an amorphous silicon layer 104 are sequentially formed on a transparent substrate 100 before the laser beam irradiating process.
A first region of FIG. 6 is a partial melting regime. When the laser beam having the energy density of a first region is irradiated on the amorphous silicon layer 104, only a surface portion xe2x80x9cSxe2x80x9d of amorphous silicon layer 104 is melted as shown in FIG. 7A. Thereafter, during the annealing process, a plurality of small grains xe2x80x9cG1xe2x80x9d are formed in a vertical direction from the lower part of the amorphous silicon layer 104.
A second region of FIG. 6 is a near-complete melting regime. When the laser beam having the energy density of a second region is irradiated on the amorphous silicon layer 104, almost all of the amorphous silicon is melted, as shown in FIG. 7B, and a plurality of seeds 103 are formed between the amorphous silicon layer 104 and the buffer layer 102. Due to the plurality of seeds 103, the silicon grains tend to grow horizontally. However, since the plurality of seeds 103 are distributed randomly over the transparent substrate 100, it is very difficult to obtain a plurality of grains xe2x80x9cG2xe2x80x9d uniformly although the grains xe2x80x9cG2xe2x80x9d are rather large.
A third region of FIG. 6 is a complete melting regime. When the laser beam having the energy density of a third region is irradiated on the amorphous silicon layer 104, all of the amorphous silicon is melted as shown in FIG. 7C. Then, a homogeneous nucleation is conducted during the annealing process. Therefore, a plurality of nuclei 105 are formed in the melted silicon, and fine grains xe2x80x9cG3xe2x80x9d are finally obtained.
The above-mentioned SLS method uses the energy density of laser beam corresponding to the third region of FIG. 6. A mechanism of the formation of single crystalline silicon by the SLS method will be described with reference to the attached FIGS. 8A to 8C. FIGS. 8A to 8C are plane views showing processes of manufacturing single crystalline silicon by the conventional SLS method.
In FIG. 8A, when a laser beam having the energy density of the third region of FIG. 6 is irradiated on the first region xe2x80x9cM1xe2x80x9d of an amorphous silicon layer 104, the first region xe2x80x9cM1xe2x80x9d is completely melted. Here, amorphous silicon 107 in a non-irradiated region, more particularly at the boundary of the first region xe2x80x9cM1xe2x80x9d, acts as a seed owing to lower energy density than in the first region xe2x80x9cM1xe2x80x9d. Accordingly, crystallization starts from the boundary of the first region xe2x80x9cM1xe2x80x9d, so that first grains 106a are formed in the first region xe2x80x9cM1xe2x80x9d.
Next, as shown in FIG. 8B, a laser beam having the same energy density as that in FIG. 8A is irradiated on the second region xe2x80x9cM2xe2x80x9d, which may include a part of the first region xe2x80x9cM1xe2x80x9d of FIG. 8A, and the second region xe2x80x9cM2xe2x80x9d is entirely melted. The first grains 106a formed in FIG. 8A act as a seed in this step, and the second grains 106b, which have a larger size than the first grains 106a, are formed by growing laterally from the first grains 106a. 
In FIG. 8C, a laser beam having the same energy density as that in FIGS. 8A and 8B is irradiated on the third region xe2x80x9cM3xe2x80x9d , which may include a part of the second region xe2x80x9cM2xe2x80x9d of FIG. 8B, and then the third region xe2x80x9cM3xe2x80x9d is completely melted. Here, the second grains 106b formed in the previous step act as a seed of this step. Therefore, crystallization starts from the second grains 106b in a lateral direction and the third grains 106c, which have a much larger size than the second grains 106b, are formed.
When silicon crystallized by this method is used as an active layer of thin film transistor, the crystallized silicon is single crystalline silicon, and the growing direction of the crystallized silicon is in accord with the channel direction, that is, the current path of thin film transistor. Therefore, electrical characteristics of the thin film transistor, which has the single crystalline silicon, are improved.
Accordingly, the present invention is directed to a method of manufacturing an array substrate having drive integrated circuits that substantially obviates one or more of problems due to limitations and disadvantages of the related art.
An advantage of the present invention is to provide a method of manufacturing an array substrate that increases productivity because of the shorter processes and the lower cost.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a method of manufacturing an array substrate having drive integrated circuits includes forming first and second semiconductor layers on a substrate, wherein the first and second semiconductor layers are made of single crystalline silicon; depositing an insulating material on the first and second semiconductor layers; depositing a metal on the insulating material; forming first photoresist patterns on the metal, wherein the first photoresist patterns are over the first and second semiconductors; forming first and second gate electrodes over the first and second semiconductor layers, respectively, by etching the metal, wherein the first and second gate electrodes are narrower than the first photoresist patterns; forming first and second insulator patterns on the first and second semiconductor layers, respectively, by etching the insulating material, wherein the first and second insulator patterns have substantially the same widths as the first photoresist patterns; doping n+ ions by using the first photoresist patterns as a first doping mask; ashing the first photoresist patterns, thereby the first photoresist patterns becoming a reduced first photoresist patterns, wherein the reduced first photoresist patterns have substantially the same width as the first and second gate electrodes; etching the first and second insulator patterns by using the reduced first photoresist patterns as an etching mask; doping nxe2x88x92 ions by using the reduced first photoresist patterns as a second doping mask; removing the reduced first photoresist patterns after the doping nxe2x88x92 ions; forming a second photoresist pattern, which covers the first gate electrode and the first semiconductor layer; doping p+ ions by using the second photoresist pattern and the second gate electrode as a third doping mask; and removing the second photoresist pattern after doping p+ ions.
In another aspect, a method of manufacturing an array substrate having drive integrated circuits includes forming first and second semiconductor layers on a substrate, wherein the first and second semiconductor layers are made of single crystalline silicon; depositing an insulating material on the first and second semiconductor layers; depositing a metal on the insulating material; forming first photoresist patterns on the metal, wherein the first photoresist patterns are over the first and second semiconductors; forming first and second gate electrodes over the first and second semiconductor layers, respectively, by etching the metal, wherein the first and second gate electrodes are narrower than the first photoresist patterns; doping n+ ions by using the first photoresist patterns as a first doping mask; removing the first photoresist patterns; doping nxe2x88x92 ions by using the first and second gate electrodes as a second doping mask; forming a second photoresist pattern, which covers the first gate electrode and the first semiconductor layer; doping p+ ions by using the second photoresist pattern and the second gate electrode as a third doping mask; and removing the second photoresist pattern after the doping p+ ions.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.